1. Field of the Invention
This invention relates to semiconductor devices with vertically structured or vertical-access transistors formed on a semiconductor substrate, and also relates to a fabrication method thereof.
2. Description of Related Arts
Traditionally, electronic equipment such as personal computers (PCs) and information communication apparatus or the like is typically designed to employ a power supply unit with a DC-to-DC converter built therein. In recent years, electronic equipment becomes smaller in size and lower in its drive voltage while its drive current becomes larger. With this trend, a power supply unit is desired which is capable of efficiently flowing a large current and also offering the handleability of higher frequencies. Thus it is required that power semiconductor devices for use in such power supply unit be low in turn-on resistance while at the same time offering enhanced switching performance at high speeds.
A typical prior known approach to meet the requirements is to use Schottky diodes as rectifier circuit elements in this type of power supplies. In contrast, a recently popularized approach to enabling flow of a large current at further lower voltages is to employ power metal oxide semiconductor field effect transistors (MOSFETs) as the rectifying devices in place of the Schottky diodes. More specifically, for power supply units, rectifier power MOSFETs are used in addition to switching power MOSFETs which switch between an input and output. These power supplies are generally called synchronous rectifier circuit scheme-type power supplies in view of the fact that switching operations are generally performed while letting rectifying power MOSFETs operate in a way synchronized with switching power MOSFETs.
FIG. 29 is an enlarged cross-sectional view of one prior art power MOSFET (for example, Published Unexamined Japanese Patent Application Nos. 2002-158353 and 2002-26321). The power MOSFET of FIG. 29 has a symmetrical structure with a dash-dot line as its boundary. When looking at part on the left side of this dash-dot line, the structure of this power MOSFET will be explained as follows. On a semiconductor substrate 1001 of heavily-doped p (p+) conductivity type, a lightly-doped p (p−) type epitaxial layer 1002 is formed. A plurality of unit cells are disposed and formed in this p−-type layer 1002, thereby making up a MOSFET. More specifically, a p-type base layer 1003 is formed in the p−-type layer 1002, with an n+-type source layer 1004 being formed within the p-type base layer 1003 and with an n-type drain layer 1005 formed outside the p-type base layer 1003. The n-type drain layer 1005 involves an n-type high-resistance drain layer 1005a and an n+-type low-resistance drain layer 1005b. 
At a p-type layer surface portion between the source layer 1004 and the drain layer 1005, a gate electrode 1007 is formed with a gate dielectric film 1006 interposed therebetween. An electrically shorting electrode 1008 is formed, which is in contact with the source layer 1004 and p-type base layer 1003. To connect this “short” electrode 1008 to the substrate 1001 with low resistance therebetween, a p+-type diffusion layer 1012 is formed to a depth reaching the substrate 1001. A source electrode 1011 is formed on the bottom or back surface of the substrate 1001. The surface on which the gate electrode 1007 is formed is covered with an interlayer dielectric film 1009, on which film a drain electrode 1010 is formed. The drain electrode 1010 is made up of a first-layer metal 1010a and a second-layer metal 1010b. The first metal 1010a is formed simultaneously during formation of the short electrode 1008 so that it comes into contact with the n+-type drain layer 1005b. The second metal 1010b is formed on the interlayer dielectric film 1009.
Additionally, a MOSFET is known which has a reverse structure that is opposite in source electrode and drain electrode positions to the MOSFET shown in FIG. 29 with a silicide layer formed on or above contact portions between the source electrode and the epitaxial layer and also above the gate electrode (as disclosed for example in U.S. Pat. No. 6,218,712).
In the vertically structured or “vertical access” MOSFET of FIG. 29, the short electrode 1008 that electrically shortcircuits together the source layer 1004 and the p-type base layer 1003 is formed on the surface of epitaxial layer 1002 in order to form the source electrode 1011 on the back surface of the substrate 1001. Additionally the p+-type diffusion layer 1012 is formed to connect this short electrode 1008 to the substrate 1001. Since the p+-type layer 1012 is a deep diffusion layer to be formed by impurity diffusion for an increased length of time period, it significantly expands in the lateral direction also. However, this p+ layer 1012 must be designed so that it does not reach a channel region. When taking into consideration both the lateral expansion of the p+ layer 1012 and the required margin space or clearance with respect to the channel region, it is a must to enlarge the width of unit cells. An increase in unit cell width would result in an increase in area of the MOSFET. When the MOSFET area is limited, the unit cells that can be laid out within the MOSFET decrease in number. This makes it difficult to sufficiently satisfy two trade-off characteristics, that is, low turn-on resistance and high-speed switching performance.